17.3 TLB Refill Vector Selection

Watch Exception

A Watch exception occurs when a load or store instruction references the physical address specified in the WatchLo/WatchHi System Control Coprocessor (CP0) registers. The WatchLo register specifies whether a load or store initiated this exception.

The CACHE instruction never causes a Watch exception.

The Watch exception is postponed if either the EXL or ERL bit is set in the Status register. If either bit is set, the instruction referencing the WatchLo/WatchHi address is executed and the exception is delayed until the delay condition is cleared; that is, until ERL and EXL both are cleared (set to 0). The EPC contains the address of the next unexecuted instruction.

A delayed Watch exception is cleared by system reset or by writing a value to the WatchLo register.*1

Watch is maskable by setting the EXL or ERL bits in the Status register.

Processing

The common exception vector is used for this exception, and the Watch code in the Cause register is set.

Servicing

The Watch exception is a debugging aid; typically the exception handler transfers control to a debugger, allowing the user to examine the situation.

To continue program execution, the Watch exception must be disabled to execute the faulting instruction. The Watch exception must then be reenabled. The faulting instruction can be executed either by interpretation or by setting breakpoints.